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| 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) FEATURES: 1 Sp ec ifi ca tio ns * * * * * * * * * * Single 3.0-Volt Read and Write Operations * Separate Memory Banks by Address Space - Bank1: 4Mbit (256K x 16 / 512K x 8) Flash - Bank2: 12Mbit (768K x 16 / 1536K x 8) Flash - Simultaneous Read and Write Capability Read Access Time - 80 ns Latched Address and Data End of Write Detection - Toggle Bit / Data # Polling / RY/BY# Write Protection by WP# pin Erase Verify Mode Flash Bank: Two Small Erase Element Sizes - 1K Words per Sector or 32K Words per Block - Erase either element before Word Program CMOS I/O Compatibility Packages Available - 48-Pin TSOP (12mm x 20mm) Continuous Hardware and Software Data Protection (SDP) * Superior Reliability - Endurance: 100,000 Cycles (Erase Verify Mode) 10,000 Cycles - Data Retention: 10 years * Low Power Consumption - - - - Active Current, Read: Active Current, Read & Write: Standby Current: Auto Low Power Mode Current: 10 mA (typical) 30 mA (typical) 5A (typical) 5A (typical) * Fast Write Operation - Chip Erase + Program: - Block Erase + Program: - Sector Erase + Program: 15 sec (typical) 500 ms (typical) 30 ms (typical) * Fixed Erase, Program, Write Times - Does not change after cycling Product Description The LE28DW1621T consists of two memory banks, Bank1 is a 256K x 16 bits or 512K x 8 sector mode flash EEPROM and Bank2 is a 768K x 16 bits or 1536K x 8 sector mode flash EEPROM, manufactured with SANYO's proprietary, high performance FlashTechnology. The LE28DW1621T writes with a 3.0-volt-only power supply. The LE28DW1621T is divided into two separate memory banks. Bank1 contains 256 sectors of 1K words or 8 blocks of 32K words, Bank2 contains 768 sectors of 1K words or 24 blocks of 32K words. Any bank may be used for executing code while writing data to a different bank. Each memory bank is controlled by separate Bank selection address (A18,A19) lines. The LE28DW1621T inherently uses less energy during Erase, and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the Flash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The Auto Low Power mode automatically reduces the active read current to approximately the same as standby; thus, providing an average read current of approximately 1 mA/MHz of Read cycle time. The Flash technology provides fixed Erase and Program times, independent of the number of erase/program cycles that have occurred. Therefore the system software or hardware does not Pr el im in ar y have to be modified or derated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated erase/program cycles. Device Operation The LE28DW1621T operates as independent 4Megabit and 12Megabit Word Pogram, Sector Erase flash EEPROMs. Two memory Banks are spareted by the address space. The Bank1 is assigned as C0000h to FFFFFh, Bank2 is assigned as 00000h to BFFFFh. All memory banks share common I/O lines, WE#, and OE#. Memory bank selection is by bank select address(A19, A18). WE# is used with SDP to control the Erase and Program operation in each memory bank. The LE28DW1621T provides the added functionality of being able to simultaneously read from one memory bank while erasing, or programming to one other memory bank. Once the internally controlled Erase or Program cycle in a memory bank has commenced, a different memory bank can be accessed for read. Also, once WE# and CE# are high during the SDP load sequence, a different bank may be accessed to read. LE28DW1621T which selectes banks (A19, A18) by a address. It can be used as a normal conventinal flash memory when operats erase or program operation to only a bank at nonconcurrent operation. The device ID cannot be accessed while any bank is writing, erasing, or programming. SANYO Electric Co.,Ltd. Semiconductor Company 1-1-11 Sakata Oizumi Gunma Japan The Flash Bank product family was jointly developed by SANYO and Sillicon Storage Technology,Inc.(SST),under SST's technology license. This preliminary specification is subject to change without notice. R.1.20(4/27/2000) No.xxxx-1/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) The Auto Low Power Mode automatically puts the LE28DW1621T in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 10mA to typically 5A. The Auto Low Power mode reduces the typical IDD active read current to the range of 1mA/MHz of Read cycle time. If a concurrent Read while Write is being performed, the IDD is reduced to typically 40mA. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Read The Read operation of the LE28DW1621T Flash banks is controlled by CE# and OE#, a chip enable and output enable both have to be low for the system to obtain data from the outputs. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the timing waveforms for further details (Figure 3). When the read operation is executed without address change after power switch on, CE# should be changed the level high to low. If the read operation is executed after programing , CE# should be changed the level high to low. Write All Write operations are initiated by first issuing the Software Data Protect (SDP) entry sequence for Chip, Block, or Sector Erase. Word Program in the selected Flash bank. Word Program and all Erase commands have a fixed duration, that will not vary over the life of the device, i.e., are independent of the number of Erase/Program cycles endured. Either Flash bank may be read to another Flash Bank during the internally controlled write cycle. The device is always in the Software Data Protected mode for all Write operations Write operations are controlled by toggling WE# or CE#. The falling edge of WE# or CE#, whichever occurs last, latches the address. The rising edge of WE# or CE#, whichever occurs first, latches the data and initiates the Erase or Program cycle. For the purposes of simplification, the following descriptions will assume WE# is toggled to initiate an Erase or Program. Toggling the applicable CE# will accomplish the same function. (Note, there are separate timing diagrams to illustrate both WE# and CE# controlled Program or Write commands.) Word Program The Word Program operation consists of issuing the SDP Word Program command, initiated by forcing CE# and WE# low, and OE# high. The words to be programmed must be in the erased state, prior to programming. The Word Program command programs the desired addresses word by word. During the Word Program cycle, the addresses are latched by the falling edge of WE#. The data is latched by the rising edge of WE#. ( See Figure 4-1 for WE# or 4-2 for CE# controlled Word Program cycle timing waveforms, Table 3 for the command sequence, and Figure 15 for a flowchart. ) During the Erase or Program operation, the only valid reads from that bank are Data# Polling and Toggle Bit. The other bank may be read. The specified Chip, Block, or Sector Erase time is the only time required to erase. There are no preprogramming or other commands or cycles required either internally or externally to erase the chip, block, or sector. Erase Operations The Chip Erase is initiated by a specific six-word load sequence (See Tables 3). A Bank Erase will typically be less than 70 ms. An alternative to the Chip Erase in the Flash bank is the Block or Sector Erase. The Block Erase will erase an entire Block (32K words) in typically 15 ms. The Sector Erase will erase an entire sector (1024 words) in typically 15 ms. The Sector Erase provides a means to alter a single sector using the Sector Erase and Word Program modes. The Sector Erase is initiated by a specific six-word load sequence (see Table 3). During any Sector, Block, or Chip Erase within a bank, any other bank may be read. Chip Erase The LE28DW1621T provides a Chip Erase mode, which allows the user to clear the Flash bank to the "1"state. This is useful when the entire Flash must be quickly erased. The software Flash Chip Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protection operation. After the loading cycle, the device enters into an internally timed cycle. (See Table 3 for specific codes, Figure 5-1 for a timing waveform, Figure12 for a flowchart. ) Block Erase The LE28DW1621T provides a Block Erase mode, which allows the user to clear any block in the Flash bank to the "1"state. The software Block Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protect operation. After the loading cycle, the device enters into an internally timed Erase cycle. (See Table 3 for specific codes, Figure 5-2 for the timing waveform, and Figure 13 for a flowchart.) During the Erase operation, the only valid reads are Data# Polling and Toggle Bit from the selected bank, other banks may perform normal read. Sector Erase The LE28DW1621T provides a Sector Erase mode, which allows the user to clear any sector in the Flash bank to the "1" state. The software Sector Erase mode is initiated by issuing the 2 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-12 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-2/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) specific six-word loading sequence, as in the Software Data Protect operation. After the loading cycle, the device enters into an internally timed Erase cycle.( See Table 3 for specific codes, Figure 5-3 for the timing waveform, and Figure 14 for a flowchart.) During the Erase operation, the only valid reads are Data# Polling and Toggle Bit from the selected bank, other banks may perform normal read. Erase Verify Mode The LE28DW1621T provides a Erase Verify Mode in order to improve the erase / programming cycles over ten times greater than normal mode. The memory cell is given a optimum margin by executing Chip erase , Block erase or Sector erase after this mode is excecuted. The Erase Verify flow shoud be executed at erase operation. If verify operation becomes bad, the re-erase operation is permited within a reguration times. Refer to Fig.20 for a flowchart at Erase Verify Mode.(See Table3 for specific codes and Fig.6 for Timing waveform) When return to a normal mode from Erase Verify mode, the Erase Verify Exit command should be excuted. This command is the same as a Software ID Exit mode.(See Table 3 for specific codes and Fig10 for Timing waveforms.) Write Operation Status Detection The LE28DW1621T provides two software means to detect the completion of a Flash bank Program cycle, in order to optimize the system Write cycle time. The software detection includes two status bits : Data# Polling (DQ7) and Toggle Bit (DQ6). The end of Write Detection mode is enabled after the rising edge of WE#, which initiates the internal Erase or Program cycle. The actual completion of the nonvolatile write is a synchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system will possibly get an erroneous result, i.e. valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious device rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. There is no provision to abort an Erase or Program operation, once initiated. For the SANYO Flash technology, the associated Erase and Program times are so fast, relative to system reset times, there is no value in aborting the operation. Note, reads can always occur from any bank not performing an Erase or Program operation. Should the system reset, while a Block or Sector Erase or Word Program is in progress in the bank where the boot code is stored, the system must wait for the completion of the operation before reading that bank. Since the maximum time the system would have to wait is 25 ms (for a Block Erase), the system ability to read the boot code would not be affected. Data# Polling (DQ7) When the LE28DW1621T is in the internal Flash bank Program cycle, any attempt to read DQ7 of the last word loaded during the Flash bank Word Load cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. (See Figure 6 for the Flash bank Data Polling timing waveforms and Figure 16 for a flowchart.) Toggle Bit (DQ6) During the Flash bank internal Write cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. (See Figure 7 for Flash bank Toggle Bit timing waveforms and Figure 16 for a flowchart.) Data Protection The LE28DW1621T provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5 volts. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. The LE28DW1621T provides a protect area by hardware protection. The assigned address is the upper are of 2Mega bit in Bnak1(E0000 to FFFFFh), which is set up by WP# when low. When this operation is executed, the functions which are Sector erase, Block erase or Word program can not be accepted. When the Chip erase operation is executed, all area will be erased except protected area. Hardware Reset Function The LE28DW1621T provides a Hardware Reset function which set up by RESET# being low. RESET# pin need a low puls longer than tRP. It needs a wait priode while tRESET from Rise edge of RESET#. The data can't be guranteed to excute the Reset operation while write operation. Software Data Protection (SDP) The LE28DW1621T provides the JEDEC approved software data protection scheme as a requirement for initiating a Write, Erase, or Program operation. With this scheme, any Write operation requires the inclusion of a series of three word-load operations to precede the Word Program operation. The three- 3 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-13 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-3/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) word load sequence is used to initiate the Program cycle, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. The six-word sequence is required to initiate any Chip, Block, or Sector Erase operation. The requirements for JEDEC compliant SDP are in byte format. The LE28DW1621T is organized by word; therefore, the contents of DQ8 to DQ15 are "Don't Care"during any SDP (3-word or 6-word) command sequence. During the SDP load command sequence, the SDP load cycle is suspended when WE# is high. This means a read may occur to any other bank during the SDP load sequence. The bank reserve in SDP load sequence is reserved by the bus cycle of command materialization. If the command sequence is aborted, e.g., an incorrect address is loaded, or incorrect data is loaded, the device will return to the Read mode within TRC of execution of the load error. Concurrent Read and Write Operations The LE28DW1621T provides the unique benefit of being able to read any bank, while simultaneously erasing, or programming one other bank. This allows data alteration code to be executed from one bank, while altering the data in another bank. The next table lists all valid states. Concurrent Read/Write State Table Bank1 Read Read Writ e No O perat ion Writ e No O perat ion Bank2 No O perat ion Writ e Read Writ e No O perat ion Read 4 Product Identification Table Word Maker ID Device Code(Bank1) Device Code(Bank2) 0000H 0001H 0001H Data (Word Mode) 0062H 257EH 257DH Data (Byte Mode) 62H 7EH 7DH Device ID codes are unique to each bank. Should a chip ID be required, any of the bank IDs may be used as the chip ID. While in the read software ID mode, no other operation is allowed until after exiting these modes. Product Identification Mode Exit In order to return to the standard Read mode, the Product Identification mode must be exited. Exit is accomplished by issuing the Software ID exit command, which returns the device to normal operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. For details, (see Table 3 for software operation and Figures 9 for timing waveforms.) Note: For the purposes of this table, write means to Block, Sector, or Chip Erase, or Word Program as applicable to the appropriate bank. The device will ignore all SDP commands and toggling of WE# when an Erase or Program operation is in progress. Note, Product Identification entry commands use SDP; therefore, this command will also be ignored while an Erase or Program, operation is in progress. Product Identification The product identification mode identifies the device manufacturer as SANYO and provides a code to identify each bank. The manufacturer ID is the same for each bank; however, each bank has a separate device ID. Each bank is individually accessed using the applicable Bank Address and a software command. Users may wish to use the device ID operation to identifythe write algorithm requirements for each bank. (For details, see Table 3 for software operation and Figures 8 for timing waveforms. ) A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TSOP-I Normal Bend (12mm x 20mm) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 Figure 1 : Pin Description : TSOP-1 (12mm x 20mm) SANYO Electric Co.,Ltd. Semiconductor Company 1-1-14 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-4/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 5 Symbol A19,A18 A19-A0,A-1 A19-A15 A19-A10 DQ15-DQ0 CE# OE# WE# BY TE# RY /BY # WP# VDD Vss NC Pin Name Bank Select address Flash Bank addresses Flash Bank Block addresses Flash Bank Sector addresses Data Input/Output Chip Enable Output Enable Write Enable Byte selection Ready / Busy output Write Protect Pow er Supply Ground No Connection Unconnected Pins Function To activate the Bank1 w hen both are high, to activate the Bank2 w hen the other combination. To provide Flash Bank address To select a Flash Bank Block for erase To select a Flash Bank Sector for erase To output data during read cycle and receive input data during w rite cycle. The outputs are in tristate w hen OE# is high or CE# is high. To activate the Flash Bank w hen CE# is low. To gate the data output buffers. To control the w rite, erase or program operations. To select a Byte mode w hen low, to select a Word mode w hen high To output low w hen w rite, other case is High-Z To execute Hardw are w rite protect w hen low To provide 3.0 volts supply.(2.7volts to 3.6 volts) Table1: Pin Description Y-Decoder Charge Pump & Vref. Address Buffer & Data Latchs X-Decoder 768Kx16 or 1536K x 8 Flash Bank2 256Kx16 or 512K x 8 Flash Bank1 DQ15-DQ0 A19-A0,A-1 CE# OE# WE# WP# RY/BY# RESET# BYTE# Control Logic I/O Buffers & Data Latches Figure2-1: Functinaly Block Diagram SANYO Electric Co.,Ltd. Semiconductor Company 1-1-15 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-5/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) Bank1 FFC00h-FFFFFh FF800h-FFBFFh | | E0400h-E07FFh E0000h-E03FFh | Total256 Sector | C0C00h-C0FFFh C0800h-C0BFFh C0400h-C07FFh C0000h-C03FFh 6 Bank2 BFC00h-BFFFFh BF800h-BFBFFh BF400h-BF7FFh BF000h-BF3FFh | | | | | Total768Sector | | | | E0000h-FFFFFh:Data Protect Area | | 00C00h-00FFFh 00800h-00BFFh 00400h-007FFh 00000h-003FFh Figure 2-1: Flash Sector Structure Array Operating Mode Read Bank1 Bank2 Block Erase Bank1 Bank2 Sector Erase Bank1 Bank2 Program Bank1 Bank2 Stand-by Write Inhibit Chip Erase CE# OE# WE# DQ A19 A18 A17-A0,A-1 VIL VIL VIL VIL VIH VIH DOUT DOUT VIH VIL VIH VIH VIL VIH VIH VIL VIH VIH VIL VIH X X X A19 VIH X VIL VIH X VIL VIH X VIL VIH X VIL X X X A18 AIN AIN VIL VIL VIH VIH VIL VIL DIN DIN See Table 3 See Table 3 VIL VIL VIH VIH VIL VIL DIN DIN See Table 3 See Table 3 VIL VIL VIH VIH VIL VIH VIH X VIL VIH OE# VIL VIL X VIL VIL WE# DIN DIN High Z X DIN DQ See Table 3 See Table 3 X X See Table 3 A17-A0,A-1 Status Operating Mode Product Identification Bank1 Bank2 CE# VIL VIL VIL VIL VIH VIH DOUT DOUT VIH VIL VIH VIH X VIL A17-A1=VIL,A-1=VIL Note2) A0=VIL or VIH Note:Entering an illegal state during an Erase, Program, or Write operation will not affect the operation, i.e., the erase program, or write will continue to normal completion. Note2: Byte Mode operation Table:2 Operating Modes Selection SANYO Electric Co.,Ltd. Semiconductor Company 1-1-16 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-6/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 7 Table:3 Software Command Codes Command Code 1stBus Address Note1,4 Software ID Entry 5555 Cycle Data Note5 AA 2ndBus Address Note1,4 2AAA Cycle Data Note5 55 3rdBus Address Note1,4 5555 +BAX 5555 +BAX 5555 5555 5555 5555 5555 5555 Cycle Data Note5 90 4thBus Address Note1,4 Note2 Cycle Data Note5 5thBus Address Note1,4 Cycle Data Note5 6thBus Address Note1,4 Cycle Data Note5 Software ID Exit 5555 AA 2AAA 55 F0 Note3 Word Address 5555 5555 5555 5555 Data In AA AA AA AA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 SAX +BAX LAX +BAX 5555 5555 30 50 10 B0 Word Program Sector Erase Block Erase Chip Erase Erase Verify Entry Erase Verify Exit 5555 5555 5555 5555 5555 5555 AA AA AA AA AA AA 2AAA 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 55 A0 80 80 80 80 F0 Notes for Software Product ID Command Code: 1. Command Code Address format : A14 - A0 are in HEX code. 2.With A14 - A0 = 0; Sanyo Manufacturer Code = 0062H is read with A0 = 0 (Word Mode) Sanyo Manufacturer Code = 62H is read with A0 = 0 and A-1 = 0 (Byte Mode) Sanyo LE28DW1621T Device code 257Eh, 257Dh is read with A0 = 1. (Word Mode) Sanyo LE28DW1621T Device code 7Eh, 7Dh is read with A0 = 1 and A-1 = 0. (Byte Mode) 3.The device does not remain in software Product ID Mode if powered down. 4.Address form A15 to A17 are 'Don't Care' for Command sequences. (Word Mode) Address form A15 to A17and A-1 are 'Don't Care' for Command sequences. (Byte Mode) A19,A18 are bank selection address have been reserved in last bus cycle of Command sequence. 5.Data format DQ0 to DQ7 are in HEX and DQ8 to DQ15 are "Don't Care". 6.BAX = Bank address: A19,A18, LAX = Block address:A19 to A15, SAX = Sector address: A19 to A10. SANYO Electric Co.,Ltd. Semiconductor Company 1-1-17 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-7/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) [Absolute Maximum Stress Ratings] 8 Applied conditions greater than those listed under "absolute maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability. Storage Temperature D. C. Voltage on Any Pin to Ground Potential Transient Voltage (<20 ns) on Any Pin to Ground Potential Package Power Package Power Dissipation Capability (Ta = 25C) [Operating Range] Ambient Temperature VDD [AC condition of Test] Input Rise/Fall Time Output Load(See Figures 13 and 14) : 5 ns : CL = 30 pF : 0C to +70C : : -65C to +150C : -0.5V to VDD + 0.5V : -1.0V to VDD + 1.0V : 1.0W 2.7V to 3.6V [DC Operating Characteristics] Symbol Parameter Power Supply current Read Write Read + Erase / Program Min Max 25 50 75 Unit mA mA mA Test Condition CE# = VIL, WE# = VIH, I/O's open, Address Input = VIL/VIH, at f =10MHz, VDD = VDD(Max) CE# = WE# = VIL, OE# = VIH, VDD = VDD(Max) CE# = VIL, OE# = WE# = VIH , Address Input = VIL/VIH, at f =10MHz, WE# = VIH, VDD = VDD(Max) CE# = VIHC , VDD = VDD(Max) VIN = Vss to VDD, VDD = VDD(Max) VOUT = Vss to VDD, VDD = VDD(Max) IDD ISB ILI IOL VIL VILC VIH VIHC VOL VOH Standby current (CMOS input) 40 10 10 VDD*0.2 0.2 VDD*0.8 VDD-0.2 0.2 VDD-0.2 A A A V V V V V V Input Leak current Output Leak current Input Input Input Input Low Voltage Low Voltag (CMOS) High Voltag High Voltge (CMOS) Output Low Voltag Output High Voltag IOL = 100A, VDD = VDD(Min) IOH = -100A, VDD = VDD(Min) SANYO Electric Co.,Ltd. Semiconductor Company 1-1-18 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-8/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 9 [Recommend System Power-up Timings] Symbol TPU-READ(1) TPU-WRITE(1) Parameter Power-up to Read Operation Power-up to Write Operation Max 200 200 Units s s Note(1): This parameter is measured only for initial qualification and after a design or process change that could affect this parameter [Capacitance (Ta = 25C, f = 1MHz, other pins open)] Symbol CDQ (1) Parameter I/O Pin Capacitance Input Capacitance Test Condition VDQ = 0V VIN = 0V Max 12PF 6PF CIN(1) Note(1): This parameter is measured only for initial qualirication and after a design or process change that could affect this parameter. [Reliability Characteristic] Symbol NEND(1) Parameter Endurance Min Spec 10,000 100,000 (Erase Verify Mode) Units Cycle/Sector TDR(1) Data Retention 10 Years Note(1): This parameter is measured only for initial qualirication and after a design or process change that could affect this parameter. SANYO Electric Co.,Ltd. Semiconductor Company 1-1-19 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-9/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) [AC Characteristic] Read Cycle Timing Parameters 10 Symbol Parameter Min 80 Max Units TRC TCE TAA TOE TCLZ(1) TOLZ TCHZ (1) (1) Raed Cycle Time CE# Access Time Address Access Time OE# Access Time BE# Low to Active Output OE# Low to Active Output BE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 80 80 80 40 0 0 30 30 0 ns ns ns ns ns ns ns ns ns TOHZ(1) TOH (1) Write, Erase, Program Cycle, Timing Parameters Symbol TBP TSE TLE TBE TAS TAH TCES TCEH TWES TWEH TOES TOEH TWP TWPH TDS TDH TVDDR(1) TEVA TIDA TBUSY TRP TREADY Parameter Word Program Time Sector Erase Time Block Erase Time Bank Erase Time Address Setup Time Address Hold Time CE# Setup Time CE# Hold Time WE# Setup Time WE# Hold Time OE# High Setup Time OE# High Hold Time WE# Puls Low Width WE# Puls High Time Data Setup Time Data Hold Time VDD Rise Time Erase Verify Entry Time ID READ / Exit Cycle Time BUSY Output Time RESET Puls Width RESET Recovery Time 500 20 0 50 0 0 0 0 0 0 50 30 50 0 0.1 150 150 80 50 Min Max 20 25 25 100 Units s ms ms ms ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns s Note:(1) This parameter is measured only for initial qualification and after a desgin or process change that could affect this parameter. 10 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-10/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 11 TRC ADDRESS A19-A0 TAA CE# TCE TOE OE# VIH WE# TCHZ DQ15-DQ0 HIGH-Z TCLZ TOH DATA VALID DATA VALID HIGH-Z TOLZ TOHZ 28DW1621TS\F3_E Exsample for Word Mode, in Byte Mode A-1=Address Input Figure 3: Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A19-A0 5555 TAH TWP WE# TAS OE# TWPH TDS 2AAA 5555 ADDR TDH CE# TCES DQ15-DQ0 AA SW0 55 SW1 A0 SW2 TCEH DATA WORD (ADDR/DATA) 28DW1621TS\F4-1_E Exsample for Word Mode, in Byte Mode A-1=Address Input Figure 4-1: WE# Controlled Word Program Cycle Timing Diagram 11 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-11/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 12 INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A19-A0 5555 TAH TWP CE# TAS OE# TWPH TDS 2AAA 5555 ADDR TDH WE# TWES DQ15-DQ0 AA SW0 55 SW1 A0 SW2 TWEH DATA WORD (ADDR/DATA) 28DW1621TS\F4-2_E Exsample for Word Mode, in Byte Mode A-1=Address Input Figure 4-2: CE# Controlled Word Program Cycle Timing Diagram SIX-BYTE CODE FOR CHIP ERASE 5555 TAH TAS CE# 2AAA 5555 5555 2AAA 5555+BAX TBE ADDRESS A19-A0 OE# TWP WE# TWPH TDS TDH DQ15-DQ0 AA SW0 55 SW1 80 SW2 AA SW3 55 SW4 10 SW5 28DW1621TS\F5-1_E Exsample for Word Mode, in Byte Mode A-1= Don't care Figure 5-1: Chip Erase Cycle Timing Diagram 12 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-12/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 13 SIX-BYTE CODE FOR BLOCK ERASE 5555 TAH TAS CE# 2AAA 5555 5555 2AAA LAX+BAX TLE ADDRESS A19-A0 OE# TWP WE# TWPH TDS TDH DQ15-DQ0 AA SW0 55 SW1 80 SW2 AA SW3 55 SW4 50 SW5 28DW1621TS\F5-2_E Exsample for Word Mode, in Byte Mode A-1= Don't care Figure 5-2: Block Erase C ycle Timing Diagram SIX-BYTE CODE FOR SECTOR ERASE 5555 TAH TAS CE# 2AAA 5555 5555 2AAA SAX+BAX TSE ADDRESS A19-A0 OE# TWP WE# TWPH TDS TDH DQ15-DQ0 AA SW0 55 SW1 80 SW2 AA SW3 55 SW4 30 SW5 28DW1621TS\F5-3_E Exsample for Word Mode, in Byte Mode A-1= Don't care Figure 5-3: Sector Erase Cycle Timing Diagram 13 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-13/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 14 6 BYTE CODE FOR ERASE VERIFY ENTRY TEVA 5555 ADDRESS A19-A0 5555 TAH TAS 2AAA 5555 5555 2AAA CE# OE# TWP WE# TWPH TDS TDH DQ15-DQ0 AA SW0 55 SW1 80 SW2 AA SW3 55 SW4 B0 SW5 LE28DW1621TS\F6_E Exsample for Word Mode, in Byte Mode A-1= Don't care Figure 6: Erase Verify Entry Timing Diagram ADDRESS A19-A0 TCE CE# TOEH OE# TOE WE# TOES DQ7 Data Data# Data# Data 28DW1621TS\ F6_E Exsample for Word Mode, in Byte Mode A-1= Address Input Figure 7: Data# Polling Timing Diagram 14 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-14/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 15 ADDRESS A19-A0 TCE CE# TOEH OE# TOE TOES WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 28DW1621\F8_E Exsample for Word Mode, in Byte Mode A-1= Don't care Figure 8: Toggle Bit Timing Diagram Three-Byte Sequence for Software ID Entry ADDRESS A19-A0 5555 2AAA 5555+BAX 0000+BAX 0001+BAX CE# OE# TWP WE# TWPH DQ15-DQ0 AA SW0 55 SW1 90 SW2 TAA 0062 62 257E/257D 7E/7D (Byte Mode) TIDA (Word Mode) 28DW1621TS\F9_E Exsample for Word Mode, in Byte Mode A-1 = 0 Figure 9: Software ID Entry and Read 15 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-15/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 16 Three-Byte Sequence for Software ID Exit and Erase Verify Exit ADDRESS A19-A0 5555 2AAA 5555+BAX TIDA CE# OE# TWP WE# T WPH DQ15-DQ0 AA SW0 55 SW1 F0 SW2 28DW1621TS\F10_E Exsample for Word Mode, in Byte Mode A-1= Don't care Figure 10: Software ID Exit amd Erase Verify Exit ADDRESS A19-A0 BAX BAX TBUSY BAX BAX CE# OE# WE# RY/BY# 28DW1612TS\F11_E Exsample for Word Mode, in Byte Mode A-1= Don't care Figure 11: RY/BY# Outputt 16 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-16/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 17 RESET# TRP CE#(WE) TREADY 28DW1611\F12_E Figure 12: Reset Timing VIHT VHT INPUT REFERENCE POINTS VHT OUTPUT VLT VILT VLT 16141\168T\F10_E AC test inputs are driven at VIHT (VDD*0.9) for a logic "1"and VILT (VDD*0.1) for a logic "0" Measurement reference points for inputs and outputs are at VHT (VDD*0.7) and VLT (VDD*0.3) Input rise and fall times (10% to 90%) are <10 ns. Figure 13: AC I/O Reference Waveforms 17 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-17/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 18 VDD TO TESTER RL HIGH TO DUT CL RL LOW Figure 14: A Test Load Example 16141\168T\F11_E Chip Erase Start Block Erase Start Software Data Protect Chip Erase Command Software Data Protect Block Erase Command Wait for End of Erase (TBE, Data# Polling, or Toggle Bit) Set Block Address Chip Erase Complete Wait for End of Erase (TLE, Data# Polling, or Toggle Bit) 28DW1621\F15_E Block Erase Complete 28DW1621\F16_E Figure 15: Chip Erase Flowchart Figure 16: Block Erase Flowchart 18 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-18/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) Sector Erase Start 19 Word Program Start Software Data Protect Sector Erase Command Software Data Protect Word Program Command Set Sector Address Set Word Address Wait for End of Erase (TSE, Data# Polling, or Toggle Bit) Load Word Data Sector Erase Complete Wait for End of Program (TBP, Data# Polling, or Toggle Bit) 28DW1621\F16_E Word Program Complete 28DW1621\F18_E Figure 17: Sector Erase Flowchart Figure 18: Word Program Flowchart Internal Timer Erase, or Program, Operation Initiated Toggle Bit Erase or Program Operation Initiated Data# Polling Erase, Program Operation Initiated Wait for TBP, TSE, TLE, TBE Read a word from a chip, block, sector, or word selected Read DQ7 of the last address set (or any address within selected chip, block, sector for erase) Erase or Program Completed Read the same word again No Yes Is DQ7 same as bit loaded? No Is DQ6 the same? Erase or Program Completed Erase or Program Completed 28DW1621TS\F19_E Figure 19: End of Erase or Program Wait Options Flowchart 19 SANYO Electric Erase or Program Wait Options Flowchart Figure 16: End of Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-19/20 16 Megabit FlashBank Memory LE28DW1621T-80T (Draft3) 20 Start Set Address = 0 Counter = 0 Execute Erase Verify Entry Execute Chip or Block or Sector Erase Command Detect End of Erase Increment Counter No Read FFFFh? Yes No (Note) Counter = 100? Yes Increment Address No Last Address ? Yes Erase Error Execute Erase Verify Exit Note: The maximum value 100 of counter is the temporary data, therefore it has possibility to change the value. Erase Verify Completed Figure 20:Erase Verify Flowchart 20 SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan R.1.20(4/27/2000) No.xxxx-20/20 |
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